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? semiconductor components industries, llc, 2017 december, 2017 ? rev. 7 1 publication order number: ncp1602/d ncp1602 enhanced, high-efficiency power factor controller the 6 ? pin pfc controller ncp1602 is designed to drive pfc boost stages. it is based on an innovative v alley s ynchronized f requency f old ? back ( vsff ) method. in this mode, the circuit classically operates in cr itical conduction m ode ( crm ) when v control voltage exceeds a programmable value v ctrl,ff . when v control is below this preset level v ctrl,ff , the ncp1602 (versions [b**] and [d**]) linearly decays the frequency down to about 30 khz until v control reaches the skip mode threshold. vsff maximizes the efficiency at both nominal and light load. in particular, the stand ? by losses are reduced to a minimum. like in fccrm controllers, internal circuitry allows near ? unity power factor even when the switching frequency is reduced. housed in a tsop6 package, the circuit also incorporates the features necessary for robust and compact pfc stages, with few external components. general features ? near ? unity power factor ? critical conduction mode (crm) ? valley synchronized frequency f old ? back (vsff): low frequency operation is forced at low current levels ? works with or without a transformer w/ zcd winding (simple inductor) ? on ? time modulation to maintain a proper current shaping in vsff mode ? skip mode at very low load current (versions[ b**] and [d**]) ? fast line / load transient compensation (d ynamic r esponse e nhancer) ? valley turn ? on ? high drive capability: ? 500 ma / +800 ma ? v cc range: from 9.5 v to 30 v ? low start ? up consumption for: [**c] & [**d] versions: low vcc start ? up level (10.5 v) [**a] & [**b] versions: high vcc start ? up level (17.0 v) ? line range detection for reduced crossover frequency spread ? this is a pb ? free device safety features ? thermal shutdown ? non ? latching, over ? voltage protection ? second over ? voltage protection ? brown ? out detection ? soft ? start for smooth start ? up operation ([**c] & [**d] versions) ? over current limitation ? disable protection if the feedback pin is not connected ? low duty ? cycle operation if the bypass diode is shorted ? open ground pin fault monitoring typical applications ? pc power supplies ? lighting ballasts (led, fluorescent) ? flat tv ? all off line appliances requiring power factor correction pin connections 1 3 drv vctrl 2 cs / zcd 4 fb 6 (top view) 5 v cc tsop ? 6 sn suffix case 318g marking diagram gnd www. onsemi.com (note: microdot may be in either location) 1 xxx ayw 1 xxx = specific device code a = assembly location y = year w = work week = pb ? free package see detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet. ordering information
ncp1602 www. onsemi.com 2 device ordering information operating part number (opn) l 1 , l 2 , l 3 option marking package type shipping NCP1602ABASNT1G aba aba tsop ? 6 (pb ? free) 3000 / tape & reel ncp1602accsnt1g acc a6c ncp1602aeasnt1g aea aea ncp1602afcsnt1g afc afc ncp1602beasnt1g bea 2ea ncp1602dccsnt1g dcc dcc ncp1602dfcsnt1g dfc dfc note: other l 1 , l 2 , l 3 combinations are available upon request. product versions are coded with three letters (l 1 ,l 2 ,l 3 ). table 1. ncp1602 1 st letter coding of product versions l 1 brown ? out function skip mode function a no no b no yes (trim) c yes (trim) no d yes (trim) yes (trim) table 2. ncp1602 2 nd letter coding of product versions l 2 crm to dcm v ctrl threshold (v) t on,max,ll ( s) t on,max,hl ( s) b 1.026 25 8.33 c 1.296 25 8.33 e 1.553 12.5 4.17 f 2.079 12.5 4.17 table 3. ncp1602 3 rd letter coding of product versions l 3 v cc startup level (v) a 17.0 c 10.5
ncp1602 www. onsemi.com 3 emi filter ac line load l1 d1 q1 v in v bulk i l r sense c bulk c z r z c p r cs1 r cs2 c in r fb2 r fb1 1 2 34 5 6 fb vctrl cs / zcd gnd drv vcc r cszcd figure 1. ncp1602 application schematic table 4. detailed pin description pin number name function 1 vctrl the error amplifier output is available on this pin. the network connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 hz to achieve high power factor ratios. vctrl pin is internally pulled down when the circuit is off so that when it starts operation, the power increases slowly to provide a soft ? start function. vctrl pin must not be controlled or pulled down externally. 2 gnd connect this pin to the pfc stage ground. 3 cs / zcd this pin monitors the mosfet current to limit its maximum current. this pin is the output of a resistor bridge connected between the drain and the source of the power mosfet. internal circuitry takes care of extracting v in , v out , i ind and zcd 4 drv the high ? current capability of the totem pole gate drive ( ? 0.5/+0.8a) makes it suitable to effectively drive high gate charge power mosfets. 5 vcc this pin is the positive supply of the ic. the circuit starts to operate when vcc exceeds 17.0 v ([**a] versions) or 10.5 v ([**c] versions) and turns off when vcc goes below 9.0 v (typical values). after start ? up, the operating range is 9.5 v up to 30 v. 6 fb this pin receives a portion of the pfc output voltage for the regulation and the dynamic response enhancer (dre) that drastically speeds ? up the loop response when the output voltage drops below 95.5% of the desired output level. fb pin voltage v fb is also the input signal for the (non ? latching) over ? voltage (ovp) and under ? voltage (uvp) comparators. the uvp comparator prevents operation as long as fb pin voltage is lower than v uvph internal voltage reference. a softovp comparator gradual- ly reduces the duty ? ratio when fb pin voltage exceeds 105% of v ref . if the output voltage still increases, the driver is immediately disabled if the output voltage exceeds 107% of the desired level (fast ovp). a 250 na sink current is built ? in to trigger the uvp protection and disable the part if the feed- back pin is accidentally open.
ncp1602 www. onsemi.com 4 table 5. maximum ratings table symbol pin rating value unit vctrl 1 v control pin ? 0.3, v ctrl,max (*) v cs/zcd 3 cs/zcd pin ? 0.3, +9 v drv 4 driver voltage driver current ? 0.3, v drv (*) ? 500, +800 v ma vcc 5 power supply input ? 0.3, + 30 v vcc 5 maximum (dv/dt) that can be applied to vcc tbd upon test engineer measurements v/s fb 6 feedback pin ? 0.3, +9 v p d r ja power dissipation and thermal characteristics maximum power dissipation @ t a = 70 c thermal resistance junction to air 550 145 mw c/w t j operating junction temperature range ? 40 to+125 c t j,max maximum junction temperature 150 c t s,max storage temperature range ? 65 to 150 c t l,max lead temperature (soldering, 10 s) 300 c msl moisture sensitivity level 1 ? esd capability, hbm model (note 1) > 2000 v esd capability, charged device model (note 1) > 1500 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *?v ctrl,max ? is the vctrl pin clamp voltage. ?v drv ? is the drv clamp voltage (v drvhigh ) if v cc is higher than (v drvhigh ). ?v drv ? is v cc otherwise. 1. this device(s) contains esd protection and exceeds the following tests: human body model 2000 v per jedec standard jesd22 ? a114e charged device model method 1500 v per jedec standard jesd22 ? c101e. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
ncp1602 www. onsemi.com 5 table 6. typical electrical characteristics (conditions: v cc = 18 v, t j from ? 40 c to +125 c, unless otherwise specified) (note 3) symbol rating min typ max unit start ? up and supply circuit v cc,on start ? up threshold, v cc increasing: [**c] versions [**a] versions 9.75 15.80 10.50 17.00 11.25 18.20 v v cc,off minimum operating voltage, v cc falling 8.50 9.00 9.50 v v cc,hyst hysteresis ( v cc ,on ? v cc ,off ) [**c] versions [**a] versions 0.75 6.00 1.50 8.00 ? ? v i cc,start maximum start ? up current, for v cc lower than 9.4 v, below startup voltage ? ? 480 a i cc,op1 operating consumption, no switching. ? 0.5 1.00 ma i cc,op2 operating consumption, 50 khz switching, no load on drv pin ? 2.00 3.00 ma frequency fold ? back dead time for configurations l 2 = b, c, e, f @ k m = 2.28 t dt,b,1 dead ? time, v ctrl = 0.65v w/ b config 5.73 7.64 9.55 s t dt,b,2 dead ? time, v ctrl = 0.75v w/ b config 2.91 3.88 4.85 s t dt,c,1 dead ? time, v ctrl = 0.65v w/ c config 8.90 11.90 14.84 s t dt,c,2 dead ? time, v ctrl = 0.75v w/ c config 5.69 7.50 9.48 s t dt,e,1 dead ? time, v ctrl = 0.65v w/ e config 9.96 13.28 16.60 s t dt,e,2 dead ? time, v ctrl = 0.75v w/ e config 6.70 8.93 10.80 s t dt,f,1 dead ? time, v ctrl = 0.65v w/ f config 13.00 17.30 21.66 s t dt,f,2 dead ? time, v ctrl = 0.75v w/ f config 9.97 13.10 16.61 s crm to dcm threshold and hysteresis v ctrl,th,b v ctrl threshold crm to dcm mode w/ b config 0.923 1.026 1.129 v v ctrl,th,c v ctrl threshold crm to dcm mode w/ c config 1.16 1.29 1.43 v v ctrl,th,e v ctrl threshold crm to dcm mode w/ e config 1.398 1.553 1.708 v v ctrl,th,f v ctrl threshold crm to dcm mode w/ f config 1.865 2.08 2.29 v skip control ([b**] & [d**] versions) v skip ? h v ctrl pin skip level, v control rising 555 617 678 mv v skip ? l v ctrl pin skip level, v control falling 516 593 665 mv v skip ? hyst v ctrl pin skip hysteresis ? 30 ? mv gate drive t r output voltage rise ? time @ c l = 1 nf, 10 ? 90% of output signal ? 30 ? ns t f output voltage fall ? time @ c l = 1 nf, 10 ? 90% of output signal ? 20 ? ns r oh source resistance @ 200 mv under high vcc ? 10 ? r ol sink resistance @200 mv above low vcc ? 7 ? v drv,low drv pin level for v cc = v cc ,off +200 mv (10 k resistor between drv and gnd) 8.0 ? ? v v drv,high drv pin level at v cc = 30 v ( r l = 33 k & c l = 1 nf) 10 12 14 v regulation block v ref feedback voltage reference 2.44 2.50 2.56 v i ea error amplifier current capability, sinking and sourcing 15 20 26 a g ea error amplifier gain 110 200 290 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the above specification gives the targeted values of the parameters. the final specification will be available once the compl ete circuit characterization has been performed.
ncp1602 www. onsemi.com 6 table 6. typical electrical characteristics (conditions: v cc = 18 v, t j from ? 40 c to +125 c, unless otherwise specified) (note 3) symbol unit max typ min rating regulation block v ctrl v ctrl,min v ctrl,max vctrl pin voltage ( v ctrl ): ? @ v fb = 2 v (ota is sourcing 20 a) ? @ v fb = 3 v (ota is sinking 20 a) ? ? 4.5 0.5 ? ? v v v out, l / v ref2 ratio ( v out low detect threshold / v ref ) (guaranteed by design) ? 95.5 ? % h out, l / v ref2 ratio ( v out low detect hysteresis / v ref ) (guaranteed by design) ? 0.35 ? % i boost vctrl pin source current when ( v out low detect) is activated 147 220 277 a current sense and zero current detection blocks v cs(th) current sense voltage reference 450 500 550 mv v cs,ovs(th) current sense overstress voltage reference 675 750 825 mv t leb,ovs ?overstress? leading edge blanking time (guaranteed by design) ? 250 ? ns t leb,ocp ?over ? current protection? leading edge blanking time (guaranteed by design) ? 400 ? ns t ocp over ? current protection delay from v cs/zcd > v cs(th) to drv low (d v cs/zcd / d t = 10 v/ s) ? 40 200 ns v zcd(th)h zero current detection, v cs/zcd rising 8 35 62 mv v zcd(th)l zero current detection, v cs/zcd falling ? 68 ? 46 ? 25 mv v zcd(hyst) hysteresis of the zero current detection comparator 46 84 ? mv to discuss versus what esd protection will be used v cl(pos) cs/zcd positive clamp @ i cs/zcd = 5 ma (guaranteed by design) ? 9.5 ? v t zcd ( v cs/zcd < v zcd ( th ) l ) to (drv high) ? 60 200 ns t sync minimum zcd pulse width ? 110 200 ns t wdg watch dog timer 80 200 320 s t wdg(os) watch dog timer in ?overstress? situation 400 800 1200 s i zcd(gnd) source current for cs/zcd pin impedance testing ? 50 ? a i zcd(vcc) pull ? up current source referenced to v cc for open pin detection ? 200 ? na static ovp d min duty cycle, v fb = 3 v ( when low clamp of v ctrl is reached) ? ? 0 % on ? time control (options [*e*], [*b*], [*f*], [*c*] for maximum t on value) t on,ll,b maximum on time, avg(v cs ) = 0.9 v and v ctrl maximum (crm) 22 25 28 s t on,hl,b maximum on time, avg(v cs ) = 2.8 v and v ctrl maximum (crm) 7.49 8.33 9.16 s t on,ll,c maximum on time, avg(v cs ) = 0.9 v and v ctrl maximum (crm) 22 25 28 s t on,hl,c maximum on time, avg(v cs ) = 2.8 v and v ctrl maximum (crm) 7.49 8.40 9.16 s t on,ll,e maximum on time, avg(v cs ) = 0.9 v and v ctrl maximum (crm) 11.4 12.5 13.6 s t on,hl,e maximum on time, avg(v cs ) = 2.8 v and v ctrl maximum (crm) 3.75 4.17 4.59 s t on,ll,f maximum on time, avg(v cs ) = 0.9 v and v ctrl maximum (crm) 11.4 12.5 13.6 s t on,hl,f maximum on time, avg(v cs ) = 2.8 v and v ctrl maximum (crm) 3.75 4.20 4.59 s k ton,ll ? hl t on @ll over t on @hl ratio (all t on versions) ? 3 ? w/o specifying max t on,min means t on,min can go down to zero t on,ll,min minimum on time, avg(v cs ) = 0.9 v (not tested, guaranteed by design) ? 300 ? ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the above specification gives the targeted values of the parameters. the final specification will be available once the compl ete circuit characterization has been performed.
ncp1602 www. onsemi.com 7 table 6. typical electrical characteristics (conditions: v cc = 18 v, t j from ? 40 c to +125 c, unless otherwise specified) (note 3) symbol unit max typ min rating on ? time control (options [*e*], [*b*], [*f*], [*c*] for maximum t on value) t on,hl,min minimum on time, avg(v cs ) = 2.8 v (not tested, guaranteed by design) ? 200 ? ns feed ? back over and under ? voltage protections (ovp and uvp) r softovp ratio (soft ovp threshold, v fb rising) over v ref (or v ref2 ) (guaranteed by design) ? 105 ? % r softovp(hyst) ratio (soft ovp hysteresis) over v ref (or v ref2 ) (guaranteed by design) ? 1.87 ? % r fastovp ratio (fast ovp threshold, v fb rising) over v ref (or v ref2 ) (guaranteed by design) ? 107 ? % r fastovp(hyst) ratio (fast ovp hysteresis) over v ref (or v ref2 ) (guaranteed by design) ? 4.0 ? % v uvph uvp threshold, v fb increasing 555 612 670 mv v uvpl uvp threshold, v fb decreasing 252 303 357 mv v uvp(hyst) uvp hysteresis 273 307 342 mv i b,fb fb pin bias current @ v fb = v ov p and v fb = v uvp 50 200 450 na brown ? out protection and feed ? forward (vsns is an internal pin that replaces vsense) v boh brown ? out threshold v mains increasing, v fb based ([c**] and [d**] versions) 754 819 894 mv v bol brown ? out threshold, v mains decreasing, avg(v cs ) based ([c**] and [d**] versions) 659 737 801 mv v bo(hyst) brown ? out comparator hysteresis ([c**] and [d**] versions) 75 100 ? mv t bo(blank) brown ? out blanking time ([c**] and [d**] versions) 36 50 67 ms i vctrl(bo) vctrl pin sink current during bo condition 20 30 42 a v hl comparator threshold for line range detection, avg( v cs ) rising 1.718 1.801 1.882 v v ll comparator threshold for line range detection, avg( v cs ) falling 1.310 1.392 1.474 v v hl(hyst) comparator hysteresis for line range detection 75 400 ? mv t hl(blank) blanking time for line range detection 13 25 43 ms thermal shutdown t limit thermal shutdown threshold 150 ? ? c h temp thermal shutdown hysteresis ? 50 ? c second overvoltage protection (ovp2) v ovp2h,hl ovp2 threshold, v cs rising, k cs = 138, @ v ref2 = 2.5 v 3.048 3.175 3.302 v v ovp2l,hl ovp2 threshold, v cs falling, k cs = 138, @ v ref2 = 2.5 v 2.969 3.093 3.217 v v ovp2(hyst),hl ovp2 comparator hysteresis, k cs = 138, @ v ref2 = 2.5 v 50 100 ? mv t leb,ovp2 ovp2 leading edge blanking time, v cs rising (guaranteed by design) ? 1000 ? ns t rst(ovp2) reset timer for ovp2 latch 400 800 1200 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. the above specification gives the targeted values of the parameters. the final specification will be available once the compl ete circuit characterization has been performed.
ncp1602 www. onsemi.com 8 figure 2. ncp1602 block diagram pfcok q s r ovlflag1 off bonok stop staticovp overstress ocp fastovp second ovp ovp2 zcd dt v ref,vcc v ref v ref,xxxx vdd thermal shutdown tsd uvp bonok off staticovp off v ref fb transconductance error amplifier ovlflag1 uvlo ovp2 vcc output buffer q s r clk skipdel clk & dt managment clk dt skip internal timing ramp drv lline t on processing circuitry v cc zcd vsns drv demag & line sense fault managment drv current sense overstress ocp v ref,ovs v ref,ocp vctrl managment vregul staticovp off bonok fb managment v ref,dre v ref,fast_ovp v ref,soft_ovp v ref,uvp ovp2 pfcok fastovp softovp uvp dre v ref,lline v ref,bonok line & bo managment
ncp1602 www. onsemi.com 9 typical characteristics figure 3. start ? up threshold, v cc increasing (v cc,on ) vs. junction temperature (versions [**c]&[**d]) figure 4. start ? up threshold, v cc increasing (v cc,on ) vs. junction temperature (versions [**a]&[**b]) t j , junction temperature ( c) t j , junction temperature ( c) 120 80 60 40 20 0 ? 40 ? 60 9.75 9.95 10.15 10.35 10.55 10.75 10.95 11.15 15.8 16.3 16.8 17.3 17.8 figure 5. minimum operating voltage, v cc falling (v cc,off ) vs. junction temperature figure 6. hysteresis (v cc,on ? v cc,off ) vs. junction temperature (versions [**c]&[**d]) t j , junction temperature ( c) t j , junction temperature ( c) 8.5 8.6 8.8 8.9 9.0 9.2 9.3 9.5 0.75 1.25 1.75 2.25 2.75 figure 7. hysteresis (v cc,on ? v cc,off ) vs. junction temperature (versions [**a]&[**b]) t j , junction temperature ( c) 6 7 8 9 10 11 12 v cc(on) (v) v cc(on) (v) v cc(off) (v) v cc(hyst) (v) v cc(hyst) (v) ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 8.7 9.1 9.4 figure 8. dead ? time, v ctrl = 0.65 v w/ e config (t dt,e,1 ) vs. junction temperature t j , junction temperature ( c) 9.96 10.96 11.96 12.96 13.96 14.96 15.96 t dt,e,1 ( s) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140
ncp1602 www. onsemi.com 10 typical characteristics figure 9. dead ? time, v ctrl = 0.75 v w/ e config (t dt,e,2 ) vs. junction temperature t j , junction temperature ( c) 6.7 7.2 7.7 8.2 8.7 9.7 10.2 10.7 t dt,e,2 ( s) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 9.2 figure 10. v ctrl threshold crm to dcm mode w/ e config (v ctrl,th,e ) vs. junction temperature t j , junction temperature ( c) 1.398 1.448 1.498 1.548 1.598 1.648 1.698 v ctrl,th,e (v) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 figure 11. v crtl pin skip level, v ctrl rising (v skip ? h ) vs. junction temperature figure 12. v crtl pin skip level, v ctrl falling (v skip ? l ) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 0.555 0.575 0.595 0.615 0.635 0.655 0.675 0.516 0.536 0.556 0.576 0.596 0.616 0.636 0.656 figure 13. drv pin level for v cc = v cc,off + 200 mv (10 ? k resistor between drv and gnd) (v drv,low ) vs. junction temperature figure 14. drv pin level @ v cc = 30 v (r l = 33 k & c l = 1 nf) (v drv,high ) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 8.0 8.5 9.0 9.5 10.0 11.0 11.5 12.0 10.0 10.5 11.0 11.5 12.0 13.0 13.5 14.0 v skip ? h (v) v skip ? l (v) v drv,low (v) v drv,high (v) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 10.5 12.5
ncp1602 www. onsemi.com 11 typical characteristics figure 15. feedback voltage reference (v ref ) vs. junction temperature t j , junction temperature ( c) 120 80 60 40 20 0 ? 40 ? 60 2.44 2.46 2.48 2.50 2.52 2.54 2.56 figure 16. error amplifier current capability, sourcing (i ea1 ) vs. junction temperature t j , junction temperature ( c) 15.6 16.6 17.6 18.6 20.6 21.6 22.6 23.6 figure 17. error amplifier current capability, sinking (i ea2 ) vs. junction temperature figure 18. error amplifier transconductance (g ea ) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) ? 24 ? 23 ? 22 ? 21 ? 19 ? 18 ? 17 ? 16 110 130 150 190 210 250 270 290 v ref (vbg post) (v) i ea1 ( a) i ea2 ( a) g ea ( s) ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 19.6 ? 20 170 230 figure 19. watch dog timer duration (t wdg ) vs. junction temperature figure 20. watch dog timer duration in ?overstress? situation (t wdg(os) ) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 80 130 180 230 280 400 500 600 700 900 1000 1100 1200 t wdg ( s) t wdg(os) ( s) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 800
ncp1602 www. onsemi.com 12 typical characteristics figure 21. maximum on time, avg(v cs ) = 0.9 v & v ctrl maximum (crm) & low line for e version (t on,ll,e ) vs. junction temperature t j , junction temperature ( c) 11.4 11.9 12.4 12.9 13.4 t on,ll(e) ( s) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 figure 22. maximum on time, avg(v cs ) = 2.8 v & v ctrl maximum (crm) & high line for e version (t on,hl,e ) vs. junction temperature t j , junction temperature ( c) 3.75 3.85 3.95 4.05 4.25 4.35 4.45 4.55 t on,hl(e) ( s) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 4.15 figure 23. uvp threshold, v fb increasing (v uvph ) vs. junction temperature figure 24. uvp threshold, v fb decreasing (v uvpl ) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 120 80 60 40 20 0 ? 40 ? 60 555 575 595 615 635 655 200 220 260 280 320 340 380 400 figure 25. uvp threshold hysteresis (v uvpl(hyst) ) vs. junction temperature t j , junction temperature ( c) 200 220 260 280 300 340 380 400 v uvph (mv) v uvpl (mv) v uvpl(hyst) (mv) ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 240 300 360 240 320 360 figure 26. comparator threshold for line range detection, avg(v cs ) rising, (v hl ) vs. junction temperature t j , junction temperature ( c) 1.718 1.738 1.758 1.778 1.818 1.838 1.858 1.878 v hl (v) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 1.798
ncp1602 www. onsemi.com 13 typical characteristics figure 27. comparator threshold for line range detection, avg(v cs ) falling, (v ll ) vs. junction temperature t j , junction temperature ( c) 1.31 1.33 1.35 1.37 1.39 1.43 1.45 1.47 v ll (v) 120 80 60 40 20 0 ? 40 ? 60 ? 20 100 140 1.41 figure 28. comparator hysteresis for line range detection, (v hl(hyst) ) vs. junction temperature t j , junction temperature ( c) 120 80 60 40 20 0 ? 40 ? 60 0.075 0.125 0.175 0.225 0.325 0.375 0.425 0.475 v hlhys (v) ? 20 100 140 0.275
ncp1602 www. onsemi.com 14 detailed operating description introduction ncp1602 is designed to optimize the efficiency of your pfc stage throughout the load range. in addition, it incorporates protection features for rugged operation. more generally, ncp1602 is ideal in systems where cost ? effectiveness, reliability, low stand ? by power and high efficiency are key requirements: ? valley synchronized frequency fold ? back: ncp1602 is designed to drive pfc boost stages in so ? called v alley s ynchronized f requency f old ? back ( vsff ). in this mode, the circuit classically operates in cr itical conduction m ode ( crm ) when v ctrl exceeds a programmable value. when the v ctrl is below this preset level, ncp1602 linearly reduces the frequency down to about 33 khz before reaching the skip threshold voltage (skip mode versions [b**] and [d**]) . vsff maximizes the efficiency at both nominal and light load. in particular, stand ? by losses are reduced to a minimum. similarly to fccrm controllers, an internal circuitry allows near ? unity power factor even when the switching frequency is reduced. ? skip mode (versions [b**] and [d**]): to further optimize the efficiency, the circuit skips cycles at low load current when v ctrl reaches the skip threshold voltage. this is to avoid circuit operation when the power transfer is particularly inefficient at the cost of current distortion. this skip function is not present on versions [a**] and [c**]). ? low start ? up current and large v cc range ([**a] versions): the start ? up consumption of the circuit is minimized to allow the use of high ? impedance start ? up resistors to pre ? charge the v cc capacitor. also, the minimum value of the uvlo hysteresis is 6 v to avoid the need for large v cc capacitors and help shorten the start ? up time without the need for too dissipative start ? up elements. the [**c] version is preferred in applications where the circuit is fed by an external power source (from an auxiliary power supply or from a downstream converter). its maximum start ? up level (11.25 v) is set low enough so that the circuit can be powered from a 12 ? v rail. after start ? up, the high v cc maximum rating allows a large operating range from 9.5 v up to 30 v. ? fast line / load transient compensation (dynamic response enhancer): since pfc stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start ? up) may cause excessive over or under ? shoot. this circuit limits possible deviations from the regulation level as follows: ? ncp1602 linearly decays the power delivery to zero when the output voltage exceeds 105% of its desired level (soft ovp). if this soft ovp is too smooth and the output continues to rise, the circuit immediately interrupts the power delivery when the output voltage is 107% above its desired level. ? ncp1602, dramatically speeds ? up the regulation loop when the output voltage goes below 95.5% of its regulation level. this function is enabled only after the pfc stage has started ? up to allow normal soft ? start operation to occur. ? safety protections: permanently monitoring the input and output voltages, the mosfet current and the die temperature to protect the system from possible over ? stress making the pfc stage extremely robust and reliable. in addition to the ovp protection, the following methods of protection are provided: ? maximum current limit: the circuit senses the mosfet current and turns off the power switch if the set current limit is exceeded. in addition, the circuit enters a low duty ? cycle operation mode when the current reaches 150% of the current limit as a result of the inductor saturation or a short of the bypass diode. ? under ? voltage protection: this circuit turns off when it detects that the output voltage is below 12% of the voltage reference (typically). this feature protects the pfc stage if the ac line is too low or if there is a failure in the feedback network (e.g., bad connection). ? brown ? out detection: the circuit detects low ac line conditions and stops operation thus protecting the pfc stage from excessive stress. ? thermal shutdown: an internal thermal circuitry disables the gate drive when the junction temperature exceeds 150 c (typically). the circuit resumes operation once the temperature drops below approximately 100 c (50 c hysteresis). ? output stage totem pole: ncp1602 incorporates a ? 0.5 a / +0.8 a gate driver to efficiently drive most to220 or to247 power mosfets. ncp1602 operation modes as mentioned, ncp1602 pfc controller implements a v alley s ynchronized f requency f old ? back ( vsff ) where: ? the circuit operates in classical cr itical conduction m ode ( crm ) when v ctrl exceeds a programmable value v ctrl,th,* . ? when v ctrl is below this v ctrl,th,* , the ncp1602 linearly reduces the operating frequency down to about 33 khz ? when vctrl reaches v crtl minimum value or the v ctrl skip mode threshold, the system works in low frequency burst mode.
ncp1602 www. onsemi.com 15 high current no delay crm low current the next cycle is delayed lower current longer dead ? time timer delay timer delay high current no delay crm low current the next cycle is delayed lower current longer dead ? time timer delay timer delay figure 29. valley switching operation in crm and dcm modes as illustrated in figure 29, under high load conditions, the boost stage is operating in crm but as the load is reduced, the controller enters controlled frequency discontinuous operation. to further reduce the losses, the mosfet turns on is stretched until its drain ? source voltage is at its valley. the end of the dead time is synchronized with the drain ? source ringing. valley synchronized frequency foldback (vsff) a/ valley synchronized (vs) drv 200 ? us watchdog cs/zcd zcd timer zero current detection dead ? time (dt) ramp for dt control clock generation drv drv drv dt clk vcs int v ctrl zcd demag sensing cszcd buffer dead time generator end of demag sensing end of dead time synchronization drv drv vctrl figure 30. valley synchronized turn ? on block diagram valley synchronized is the first half of the vsff system. synchronizing the turn ? on with the drain voltage valley maximizes the efficiency at both nominal and light load conditions. in particular, the stand ? by losses are reduced to a minimum. the synchronization of power mosfet turn ? on (rising edge of clk signal) with drain voltage valley is depicted on figure 30. this method avoids system stalls between valleys. instead, the circuit acts so that the pfc controller transitions from the n valley to (n+1) valley or vice versa from the n valley to (n ? 1) cleanly as illustrated by the simulation results of figure 31. when the line voltage and inductor current are very low, or when the amplitude of the drain voltage gets too low (in the case of long dead times), the turn ? on of the power mosfet is no longer synchronized with the drain valley but will start exactly at the end of a programmed dead time looks to the zcd timer block. if no demagnetization is sensed the power mosfet will be turned ? on after a watchdog timing of 200 ? s.
ncp1602 www. onsemi.com 16 ? 0 50 100 150 200 250 300 350 2.42 2.44 2.46 2.48 2. 5 2.52 2.54 2 4 6 8 10 / 385 .69 385. 695 385 .7 385 . 705 385 .71 ? 0. 2 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2 inductor current (100 ma/div) drv (2 v/div) ramp + vffctl (20mv/div) drain source voltage (50 v/div) time (5 usecs /div) 3rd valley 4th valley v ref,dt figure 31. clean transition without hesitation between valleys b/ frequency foldback (ff) frequency foldback is the second half of the vsff system. when v ctrl falls below an option ? programmable v ctrl,th,* threshold, the ncp1602 enters dcm and linearly reduces the operating frequency down to about 33 khz by adding a dead ? time after the end of inductor demagnetization. the end of the dead ? time is synchronized with the valley in the drain voltage, hence the name v alley s ynchronized ( vs ). the lower the v ctrl value, the longer the dead ? time. the f requency f oldback ( ff ) system adjusts the on ? time versus t dt (see figure 32) and the output power in order to ensure that the instantaneous mains current is in phase with the mains instantaneous voltage (creating a pf=1). i peak ,max i ind clk dt t on t demag 0 t sw t dt time drv figure 32. ncp1602 clock, dead time and t on waveforms
ncp1602 www. onsemi.com 17 when the load is at its maximum (the maximum v ctrl value and inductor peak current limitation is not triggering), the controller runs in crm mode and the frequency (@ v in =v in,max ) has its minimum value. as we start decreasing the output power, the v ctrl voltage decreases, the switching frequency (@ v in =v in,max ) increases and the controller stays in crm mode until v ctrl reaches a threshold voltage named v ctrl,th,* . from this point, continuing to reduce the output power makes the controller to continue increase the dead time ( t dt ) after the end of demagnetization resulting in a dcm conduction mode and a switching frequency decrease ( f requency f oldback). when the output power is reduced and we enter dcm mode, the switching frequency decreases down to a value given by the following equation, which is valid down to before entering skip mode. this minimum dcm frequency value is dominated by the dead time value, t on plus t demag being negligible versus t dt that has reached is maximum value t dt,max . f sw, dcm, min 1 t dt,max t on t demag 1 t dt,max (eq. 1) in order to have, depending on customer application, a different limitation of the maximum switching frequency (@v in =v in,max ), as well as different v ctrl thresholds for crm to dcm boundary, different product versions are made available (see table 2). crm ? dcm and dcm ? crm transition hysteresis hesitation of the system to transition between the modes crm and dcm may have a consequences on inductor current shape and distort the mains current, resulting in a bad pf value when the operating point is at the crm ? dcm boundary. to avoid such undesired behavior, a 40 ? mv hysteresis is added on v ctrl threshold. the v ctrl threshold for transitioning from crm to dcm mode is named v ctrl,th, * (see t able 6) and the v ctrl threshold for transitioning from dcm to crm mode is v ctrl,th ,* + 40 mv. ncp1602 skip mode (active on versions [b**] and [d**], disabled on versions [a**] and [c**]) the circuit also skips cycles when v ctrl decreases towards v skip ? l threshold. a comparator monitors the v ctrl voltage and inhibits the drive when v ctrl is lower than the skip mode threshold v skip ? l . switching resumes when v ctrl exceeds v skip ? h threshold. the skip mode capability is disabled whenever the pfc stage is not in nominal operation (as dictated by the pfcok signal ? see pfcok operation section). ncp1602 on ? time modulation and v ton processing circuit let?s analyze the ac line current absorbed by the pfc boost stage. the initial inductor current at the beginning of each switching cycle is always zero. the coil current ramps up when the mosfet is on . the slope is ( v in / l ) where l is the coil inductance. at the end of the on ? time ( t 1 ), the inductor starts to demagnetize. the inductor current ramps down until it reaches zero. the duration of this phase is ( t 2 ). in some cases, the system enters then the dead ? time ( t 3 ) that lasts until the next clock is generated. one can show that the ac line current is given by: i in v in t 1 t 1 t 2 2t l (eq. 2) where t t 1 t 2 t 3 (eq. 3) is the switching period and v in is the ac line rectified voltage. in light of this equation, we immediately note that i in is proportional to v in if [ t 1. ( t 1 + t 2 )/ t ] is a constant. i peak,max i ind t 1 t 2 0 t t 3 v in time l1 d1 q1 v in v out i ind c bulk c in drv r sense time figure 33. pfc boost converter and inductor current in dcm
ncp1602 www. onsemi.com 18 the ncp1602 operates in voltage mode. as portrayed by figure 33 & figure 34, the mosfet on ? time t 1 is set by a dedicated circuitry monitoring v ctrl and dead ? time t dt ensuring [ t 1. ( t 1 + t 2 )/ t ] is constant and as a result making i in proportional to v in (pf=1) on ? time t 1 is also called t on and its maximum value t on,max is obtained when v ctrl is at maximum level. the internal circuitry makes t on,max at high line condition (hline) to be 3 times the t on,max at low line condition (lline) (low ? pass filtered internal cs ? pin voltage is compared to v hl and v ll for deciding whether we are in hline or in lline). two other values of t on,max are offered as options. the input current is then proportional to the input voltage. hence, the ac line current is properly shaped. one can note that this analysis is also valid in the crm case. this condition is just a particular case of this functioning where ( t 3 =0), which leads to ( t 1 + t 2 = t ) and (v ton =v regul ). that is why the ncp1602 automatically adapts to the conditions and transitions from dcm and crm (and vice versa) without power factor degradation and without discontinuity in the power delivery. c ramp i ch v ton pwm comparator turns off mosfet closed when output low v ton ramp voltage pwm output figure 34. pwm circuit and timing diagram ncp1602 regulation block and output voltage control a trans ? conductance error amplifier (ot a) with access to the inverting input and output is provided. it features a typical trans ? conductance gain of 200 s and a maximum current capability of 20 a. the output voltage of the pfc stage is typically scaled down by a resistors divider and monitored by the inverting input (pin fb). bias current is minimized (less than 500 na) to allow the use of a high impedance feed ? back network. however, it is high enough so that the pin remains in low state if the pin is not connected. the output of the error amplifier is brought to pin vctrl for external loop compensation. typically a type ? 2 network is applied between pin vctrl and ground, to set the regulation bandwidth below about 20 hz and to provide a decent phase boost. the swing of the error amplifier output is limited within an accurate range: ? it is forced above a voltage drop ( v f ) by some circuitry. ? it is clamped not to exceed 4.0 v + the same v f voltage drop. the v f value is 0.5 v typically . the regulated output voltage vout uses a reference voltage v ref = 2.5 v given the low bandwidth of the regulation loop, abrupt variations of the load, may result in excessive over or under ? shoot. over ? shoot is limited by the over ? voltage protection connected to fb pin ( feedback). ncp1602 embeds a ? d ynamic r esponse e nhancer? circuitry ( dre ) that contains under ? shoots. an internal comparator monitors the fb pin voltage ( v fb ) and when v fb is lower than 95.5% of its nominal value, it connects a 200 ? a current source to speed ? up the charge of the compensation network. effectively this appears as a 10x increase in the loop gain. the circuit also detects overshoot and immediately reduces the power delivery when the output voltage exceeds 105% of its desired level. the error amplifier ota and the ovp, uvp and dre comparators share the same input information. based on the typical value of their parameters and if (v out,nom ) is the output voltage nominal value (e.g., 390 v), we can deduce:
ncp1602 www. onsemi.com 19 ? output regulation level: v out,nom ? output dre level: v out,dre = 95.5% x v out,nom ? output soft ovp level: v out,sovp = 105% x v out,nom ? output fast ovp level: v out,fovp = 107% x v out,nom current sense and zero current detection ncp1602 is designed to monitor the current flowing through the power switch during on ? time for detecting over current and overstress and to monitor the power mosfet drain voltage during demagnetization time and dead time in order to generate the zcd signal. zcd cs/zcd pin r cs1 r cs2 c cs drv drv ocp blanking overstress ocp vsns drain source v ocp,ref vcs int v ovs,ref drv ovs blanking vcc cszcd buffer drv demag & line sense overstress timer figure 35. current sense, zero current detection blocks and vin sense current sense, zero current detection and vin sense are using the cs/zcd pin voltage as depicted in the electrical schematic of figure 35. current sense the power mosfet current i is sensed during the t on phase by the resistor r sense inserted between the mosfet source and ground (see figure 36). during t on phase r cs1 and r cs2 are almost in parallel and the signal r sense .i is equal to the voltage on pin cs. i r cs1 r cs2 c cs r sense d s cs r dson r cs1 r cs2 c cs r sense d,s cs i figure 36. current sensing during the t on phase
ncp1602 www. onsemi.com 20 during the on ? time and after a 200 ? ns blanking time, an ocp (over current protection) signal is generated by an ocp comparator, comparing ( v cs = v cs2 ) to a 500 ? mv internal reference. when r senseids_max = v cs = v cs2 = 500 mv we get: i ds_max v ocp r sense (eq. 4) when v cs exceeds the 500 ? mv internal reference threshold, the ocp signal turns high to reset the pwm latch and forces the driver low. the 200 ? ns blanking time prevents the ocp comparator from tripping because of the switching spikes that occur when the mosfet turns on. zero current detection the cs pin is also designed to receive, during t demag and t dt , a scaled down (divided by 138) power mosfet drain voltage that will be used for zero current detection. it may happen that the mosfet turns on while a huge current flows through the inductor. as an example such a situation can occur at start ? up when large in ? rush currents charge the bulk capacitor to the line peak voltage. traditionally, a bypass diode is generally placed between the input and output high ? voltage rails to divert this inrush current. if this diode is accidently shorted, the demagnetization will be impossible and cycle after cycle the inductor current will increase so the mosfet will also see a high current when it turns on. in both cases, the current can be large enough to trigger the overstress (ovs) comparator. in this case, the ?overstress? signal goes high and disables the driver for an 800 ? s delay. this long delay leads to a very low duty ? ratio operation in case of ?overstress? fault in order to limit the risk of overheating. when no signal is received that triggers the zcd comparator to indicate the end of inductor demagnetization, an internal 200 ? s watchdog timer initiates the next drive pulse. at the end of this delay, the circuit senses the cs/zcd pin impedance to detect a possible grounding of this pin and prevent operation. brown ? out detection (versions [c**] and [d**]) for an application w/o vaux (using the drain) and using brown ? out options ([c**] and [d**]) the brown ? out feature will use the high and low brown ? out levels. brown ? out options ([c**] and [d**]) must not be used on an application using vaux as these options are not designed to work in this case. by default, the brown ? out flag is set high (bonok=1), meaning that v in ,sensed thru cszcd pin and v sns (v sns is a low ? pass filtered scaled down v in ) internal signal (see figure 1), when higher than internal reference voltage v boh will set the brown ? out flag to zero (bonok=0) and allow the controller to start. after bonok is set to zero, and switching activity starts, the v in continues to be sensed thru cszcd pin and when v sns falls under brown ? out internal reference voltage v bol for 50 ms, bonok flag will be set to 1. after bonok flag will be set to 1, drive is not disabled, instead, a 30 ? a current source is applied to vctrl pin to gradually reduce v ctrl . as a result, the circuit only stops pulsing when the staticovp function is activated (that is when v ctrl reaches the skip detection threshold). at that moment, the circuit stops switching. this method limits any risk of false triggering. for an application w/ vaux (not using the drain), brown ? out options ([c**] and [d**]) are not be allowed and the uvp will act like a brown ? in. the reason is that before controller starts switching, the v out voltage is equal to v mains,rms and sensed by fb pin and compared to uvp high internal reference voltage v uvph . the input of the pfc stage has some impedance that leads to some sag of the input voltage when the input current is large. if the pfc stage suddenly stops while a high current is drawn from the mains, the abrupt decay of the current may make the input voltage rise and the circuit detect a correct line level. instead, the gradual decrease of v control avoids a line current discontinuity and limits the risk of false triggering. v sns internal voltage is also used to sense the line for feed ? forward. a simil ar method is used: ? the v sns internal pin voltage is compared to a 1.801 ? v reference. ? if v sns exceeds 1.801v, the circuit detects a high ? line condition and the loop gain is divided by three (the internal pwm ramp slope is three times steeper) ? once this occurs, if v sns remains below 1.392 v for 25 ms, the circuit detects a low ? line situation (500 ? mv hysteresis). at startup, the circuit is in high ? line state (?lline? low?) and then v sns will be used to determine the high ? line or low ? line state. the line range detection circuit allows more optimal loop gain control for universal (wide input mains) applications.
ncp1602 www. onsemi.com 21 v ref,lline v ref,bonok csint vsns 1.801 v if lline=1 1.392 v otherwise 0.819 v if bonok=1 0.737 v otherwise cszcd buffer demag & line sense drv figure 37. input line sense monitoring thermal shut ? down (tsd) an internal thermal circuitry disables the circuit gate drive and keeps the power switch off when the junction temperature exceeds 150 c. the output stage is then enabled once the temperature drops below about 100 c (50 c hysteresis). the temperature shutdown remains active as long as the circuit is not reset, that is, as long as v cc is higher than a reset threshold. output drive section the output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. its high current capability ( ? 500 ma / +800 ma) allows it to effectively drive high gate charge power mosfet. second over ? voltage protection on top of the existing overvoltage protection, a second and redundant overvoltage protection named ovp2 has been added. this overvoltage protection, senses, during t demag the value of v out , thru the r cs1 , r cs2 divider bridge connected to the pin cs and compares it to an ovp2 voltage reference v ref,ovp2 . because it is not possible to adjust the v ref,ovp2 reference to r fb1 & rf b2 that programs the v out value, it has been decided to set v ref,ovp2 and r cs1 , r cs2 in order to get ovp2 triggering for vout voltages much higher than for ovp condition (e.g. ovp2 goes high when vout goes higher than 438 v) for v out = 438 v for ovp2 and given a k cs value equal to 1/138 (k cs =r cs2 /(r cs1 +r cs2 ), this gives v ref,ovp2 = 3.175 v for the threshold voltage to which is compared to the cs voltage during t off . when v cs goes above v ref,ovp2 threshold of the ovp2 comparator (100 mv hysteresis), and after a 1 ? s leading edge blanking time, the ovp2 flag is latched and will stop the switching by resetting the main pwm latch. the ovp2 latch is reset each 800 s. off mode as previously mentioned, the circuit turns off when one of the following faults is detected: ? incorrect feeding of the circuit (?uvlo? high when v cc < v cc ( off ) , v cc ( off ) equating 9 v typically). ? excessive die temperature detected by the thermal shutdown ? under ? voltage protection ? brown ? out fault and staticovp (see figure 2) generally speaking, the circuit turns off when the conditions are not proper for desired operation. in this mode, the controller stops operating. the major part of the circuit sleeps and its consumption is minimized. more specifically, when the circuit is in off state: ? the drive output is kept low ? all the blocks are off except: ? the uvlo circuitry that keeps monitoring the v cc voltage and controlling the start ? up current source accordingly. ? the tsd (thermal shutdown) ? the under ? voltage protection (?uvp?) ? the brown ? out circuitry ? v ctrl is grounded so that when the fault is removed, the device starts ? up under the soft start mode. ? the internal ?pfcok? signal is grounded. ? the output of the ?v ton processing block? is grounded
ncp1602 www. onsemi.com 22 failure detection when manufacturing a power supply, elements can be accidentally shorted or improperly soldered. such failures can also happen to occur later on because of the components fatigue or excessive stress, soldering defaults or external interactions. in particular, adjacent pins of controllers can be shorted; a pin can be grounded or badly connected. such open/short situations are generally required not to cause fire, smoke nor big noise. ncp1602 integrate functions that ease meet this requirement. among them, we can list: ? floating feedback pin a special internal circuitry detects the floating feedback pin and stops the operation of the ic. ? fault of the gnd connection if the gnd pin is not connected, internal circuitry detects it and if such a fault is detected for 200 s, the circuit stops operating. ? detection the cs/zcd pin improper connection if the cs/zcd pin is floating or shorted to gnd it is detected by internal circuitry and the circuit stops operating. ? boost or bypass diode short the controller addresses the short situations of the boost and bypass diodes (a bypass diode is generally placed between the input and output high ? voltage rails to divert this inrush current). practically, the overstress protection is implemented to detect such conditions and forces a low duty ? cycle operation until the fault is gone. refer to application note andxxxx for more details.
ncp1602 www. onsemi.com 23 package dimensions tsop ? 6 case 318g ? 02 issue v *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 13: pin 1. gate 1 2. source 2 3. gate 2 4. drain 2 5. source 1 6. drain 1 recommended 0.60 6x 3.20 0.95 6x 0.95 pitch dimensions: millimeters 23 4 5 6 d 1 e b e1 a1 a 0.05 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimensions d and e1 are determined at datum h. 5. pin one indicator must be located in the indicated zone. c dim a min nom max millimeters 0.90 1.00 1.10 a1 0.01 0.06 0.10 b 0.25 0.38 0.50 c 0.10 0.18 0.26 d 2.90 3.00 3.10 e 2.50 2.75 3.00 e 0.85 0.95 1.05 l 0.20 0.40 0.60 0.25 bsc l2 ? 0 1 0 1.30 1.50 1.70 e1 e note 5 l c m h l2 seating plane gauge plane detail z detail z m on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1602/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ?

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